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    • 专利摘要:
    The invention relates to a method for manufacturing a gate-effect field effect transistor (41), comprising: -providing a superposition of first to third nanowires (11-17), each made of semiconductor material, the second nanowire being stressed along its longitudinal axis, the middle portion of the first to third nanowires being covered by a sacrificial gate (31); -forming recesses by removing an intermediate portion of the first and third nanowires (11, 13) between their ends and their median part, while maintaining the superposition of the first to third nanowires (11, 12, 13) at the ends and under the sacrificial gate (31); forming an electrical insulator in said recesses around the second nanowire (12); removing said sacrificial gate (31) and the median portion of the first and third nanowires (11, 13); forming a gate electrode encapsulating the middle portion of said second nanowire (12).
    公开号:FR3057703A1
    申请号:FR1659942
    申请日:2016-10-13
    公开日:2018-04-20
    发明作者:Emmanuel Augendre；Remi COQUAND；Shay REBOH
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    Holder (s): COMMISSIONER OF ATOMIC ENERGY AND ALTERNATIVE ENERGIES Public establishment.
    Extension request (s)
    Agent (s): INNOVATION COMPETENCE GROUP.
    y PROCESS FOR MANUFACTURING A COATING GRID FIELD-EFFECT TRANSISTOR.
    FR 3,057,703 - A1 (5 // The invention relates to a method for manufacturing a field effect transistor with a covering gate (41), comprising:
    -provide a superposition of first to third nanowires (11-17), each of semiconductor material, the second nanowire being subjected to a stress along its longitudinal axis, the middle part of the first to third nanowires being covered by a sacrificial grid ( 31);
    -forming recesses by withdrawal of an intermediate part of the first and third nanowires (11, 13) between their ends and their middle part, retaining the superposition of the first to third nanowires (11,12,13) at the ends and under the sacrificial grid (31);
    forming an electrical insulator in said recesses around the second nanowire (12);
    -removing said sacrificial grid (31) and the middle part of the first and third nanowires (11, 13);
    -forming a gate electrode coating the middle part of said second nanowire (12).
    100
    METHOD FOR MANUFACTURING A COATING GRID FIELD-EFFECT TRANSISTOR
    The invention relates to field effect transistors with a covering grid, and in particular to the manufacturing methods for such transistors.
    The increase in the performance of integrated circuits due to the miniaturization of field effect transistors is faced with a technological and scientific obstacle. One of the issues is the increase in static and dynamic power in integrated circuits. In order to reduce this power consumption, new architectures and new materials which will make it possible to obtain a low operating voltage are today intensively studied.
    In particular, for technological nodes below 50 nm, the electrostatic control of the channel by the gate becomes a predominant operating parameter for the operation of the transistor. To improve this electrostatic control, various technologies of multi-gate transistors are the subject of developments, in particular the transistors with a covering gate. Furthermore, it is known to constrain the pMOS transistor channels in compression or the nMOS transistor channels in voltage according to their direction of conduction, so as to improve the mobility of the carriers in these channels.
    A known manufacturing method for a pMOS transistor with a covering gate is as follows. A stack of nanowires is formed, comprising an alternation of silicon nanowires and silicon-germanium on a substrate, so as to obtain, for example, SiGe nanowires constrained in compression and relaxed silicon nanowires. A sacrificial grid is formed to cover the middle part of the stack of nanowires. Insulating spacers are also formed on either side of the sacrificial grid, to cover an intermediate middle part of the stack of nanowires. The channels of the transistor are intended to be formed in this middle part. The nanowire parts of the stack projecting beyond the spacers are not covered and are removed by etching. The SiGe nanowires are then relaxed and the silicon nanowires then undergo a stress in tension.
    The part of the silicon-germanium nanowires placed under the spacers is removed by selective etching, so as to form cavities under these spacers. Internal spacers are then placed inside the cavities. By a silicon-germanium growth step by epitaxy, a source and a drain are formed on either side of the stack. The source and the drain formed by epitaxy are then in contact and in the continuity of the silicon nanowires which have been preserved under the sacrificial grid and the spacers. The source and the drain are then encapsulated in a passivation or encapsulation material.
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    A groove is then formed at the sacrificial grid and the sacrificial grid is removed. The residual stack of nanowires is then discovered. By selective etching, the silicon-germanium nanowires are removed. A gate insulator is then deposited on the exposed part of the silicon nanowires, then a gate material is formed on the gate insulator to encapsulate the middle part of these nanowires. At the end of this manufacturing process, the silicon nanowires remain slightly stressed in voltage in the channel, which degrades the performance of the pMOS transistor.
    Similarly, for an nMOS transistor of the sSOI type, or based on an SRB layer, a similar manufacturing process results in a relaxation of the silicon of the channel, despite an initial voltage prestress in the silicon nanowires. The performance of such an nMOS transistor is therefore degraded.
    The subsequent formation of the source and the drain by epitaxy does not make it possible to obtain the desired stress in the channel zone of the silicon nanowires.
    There is therefore a need for a method of manufacturing a field effect transistor with a coated gate, intended to obtain a significant stress in its channels. The invention aims to solve one or more of these drawbacks. The invention thus relates to a method for manufacturing a field effect transistor with a covering gate, comprising the steps of:
    -provide a substrate surmounted by a superposition of first to third nanowires each having a middle part and first and second ends on either side of the middle part along a longitudinal axis, each of these nanowires being formed of semi-material conductive, said second nanowire being disposed between the first and third nanowires and being formed in a semiconductor material different from that of the first nanowire and different from that of the third nanowire, so that the first or second nanowire is subjected to a stress mechanical along its longitudinal axis, the middle part of the first to third nanowires being covered by a sacrificial grid, electrical insulation coating an intermediate part of the second nanowire between its middle part and its first end and between its middle part and its second end , said electrical insulator separating the first end of the middle tie of the first and third nanowires, and separating the second end from the middle part of the first and third nanowires;
    - removal of the first and second ends of the first and third nanowires;
    depositing a semiconductor material different from that of the first to third nanowires, by growth by epitaxy from the first and second ends of the second nanowire, so as to modify the mechanical stress in the middle part of the second nanowire; then
    ICG11092 EN Text Depot.docx
    -removing said sacrificial grid and removing the middle part of the first and third nanowires;
    -forming a gate electrode coating the middle part of said second nanowire.
    The invention also relates to the following variants. Those skilled in the art will understand that each of the characteristics of the following variants can be combined independently with the above characteristics, without however constituting an intermediate generalization.
    According to a variant, said first to third nanowires supplied include silicon, the first and third nanowires including a proportion of germanium greater than that of the second nanowire.
    According to another variant, the first and third nanowires supplied are made of Si (ix) Ge x with 0.2 <x <0.6.
    According to another variant, said deposited semiconductor material is SiC doped in situ with Phosphorus.
    According to yet another variant, said deposited semiconductor material is SiGe doped in situ with Boron.
    Alternatively, said deposited semiconductor material has a higher concentration of Germanium than that of the first and third nanowires.
    According to another variant, said second nanowire of the supplied substrate is relaxed.
    According to yet another variant, said second nanowire of the supplied substrate is stressed in tension along its longitudinal axis.
    According to yet another variant, the method comprises preliminary steps of:
    -Removal of intermediate parts of first and third nanowires initially continuous, between their first end and their middle part on the one hand, and between their second end and their middle part on the other hand;
    -deposit of said insulator.
    According to another variant, said step of removing the intermediate parts of the first and third nanowires comprises an ion implantation in these intermediate parts then a step of selective etching of these parts.
    According to yet another variant, said step of removing the intermediate parts of the first and third nanowires comprises an etching of said intermediate parts of the first and third nanowires according to their crystal planes.
    According to yet another variant, the method further comprises a step of doping the second nanowire in an intermediate part between its first end and its middle part and in an intermediate part between its second end and its middle part, after the stage of supply of the substrate and prior to the step of removing the sacrificial grid.
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    According to a variant, said first to third nanowires supplied have a thickness at most equal to 15 nm.
    According to another variant, said electrical insulator for the supplied substrate has a thickness of between 3 and 15 nm between the first end and the middle part of the first and third nanowires.
    Other characteristics and advantages of the invention will emerge clearly from the description given below, by way of indication and in no way limitative, with reference to the appended drawings, in which:
    FIGS. 1 to 28 illustrate a transistor during different stages of its manufacturing process, according to an example of an embodiment of the invention.
    The invention proposes a method for manufacturing a field effect transistor with a covering grid, which makes it possible on the one hand to form internal spacers when nanowires are kept between a source zone and a drain zone passing through a channel zone, and on the other hand allowing high prestressing to be obtained inside these channel zones. In general, a voltage preload will be maintained for the channel region of an nMOS transistor and a compression preload for the channel region of a pMOS transistor.
    Figures 1 to 28 illustrate a transistor 1 at different stages of its manufacturing process, according to an exemplary embodiment of the invention. The manufacturing process is applied here for an nMOS transistor. The steps described with reference to FIGS. 1 to 5 are known per se to those skilled in the art and given by way of nonlimiting example for obtaining a superposition of nanowires with a sacrificial grid.
    In FIG. 1, there is a substrate, illustrated in perspective. In the example detailed here, the substrate can for example be of the sSOI type (for strained silicon on insulator) or of the SRB type (for substrate with relaxed buffer layer), in a manner known per se. The substrate is here of semiconductor on insulator type.
    The substrate here comprises an insulating layer 100, covered with a semiconductor layer 101. The semiconductor layer 101 is here a relaxed SiGe layer. For an SRB type substrate, the insulating layer 100 will for example be replaced by a relaxed SiGe layer covered with a silicon layer typically comprising a biaxial tension stress.
    In Figure 2, we proceeded to the formation of a superposition of layers
    102 to 107 on the layer of SiGe 101. An alternation of layers of SiGe 101, 103, 105 and 107 and of layers of silicon 102, 104 and 106 has thus been formed. The layers 102 to 107 are typically formed by steps sequential of
    ICGl 1092 EN Depot Texte.docx deposit by epitaxy. In a manner known per se, due to the differences in lattice parameters between the silicon layers 102, 104 and 106, and the SiGe layers 101, 103, 105 and 107, a voltage stress is induced in the Si 102 layers , 104 and 106.
    The thickness of the layers 101, 103, 105 and 107 is for example between 5 and 15 nm, preferably at most 10 nm. This thickness is for example 7 nm. The thickness of the layers 102, 104 and 106 is for example between 5 and 15 nm, preferably at most 10 nm. This thickness is for example 9 nm.
    In FIG. 3, a mask 2 has been formed on the superposition of the layers 101 to 107, for example by photolithography. In FIG. 4, the layers 101 to 107 were etched, so as to form superpositions or stacks of adjacent nanowires. Each superposition or stack of nanowires comprises a superposition of nanowires 11 to 17. The nanowires 11 to 17 extend in a longitudinal direction, and thus have a length at least twice greater than their width or their height. The nanowires 11, 13, 15 and 17 are here in SiGe, for example
    If (ix) Ge x with 0.2 <x <0.6. We can for example take the value x = 0.3. The nanowires 12, 14 and 16 are here made of silicon. Mask 2 has been removed from the stacks. The width of each stack is for example between 10 and 50 nanometers. The nanowire stacks here comprise 7 superimposed nanowires. A different number of superimposed nanowires can of course be used. The height of the nanowire stacks is for example between 30 and 100 nanometers. At this stage, the SiGe nanowires 11, 13, 15 and 17 are relaxed and the silicon nanowires 12, 14 and 16 are stressed in tension.
    In FIG. 5, a sacrificial grid 31 has been formed for each of the nanowire stacks. Each sacrificial grid 31 coats the middle part of a respective stack of nanowires. The sacrificial grid 31 comprises for example a protective layer with a thickness of between 1 nm and 3 nm of S1O2 in contact with the nanowires, covered with a layer of Poly Si. The sacrificial grid 31 can also be formed (so nonlimiting) with a single layer of SiO2. The process for forming and shaping each sacrificial grid 31 is known per se. The gate length of a transistor to be formed is defined by the length over which a sacrificial gate 31 coats a respective stack of nanowires.
    In FIG. 6, sacrificial spacers 32 and 33 have been formed, on either side of each of the sacrificial grids 31. The sacrificial spacers 32 each coat a respective stack of nanowires at its middle part, on one side a respective sacrificial grid 31. The sacrificial spacers 33 each coat a respective stack of nanowires at the level of
    ICG11092 FR Depot Texte.docx its middle part, on the other side of a respective sacrificial grid 31. The process for forming and shaping each sacrificial spacer 32,33 is known per se. The width of each of the sacrificial spacers 32 or 33 is for example between 3 and 15 nm. The sacrificial spacers 32,33 are for example made of dielectric material. The sacrificial spacers 32 or 33 are for example formed from SiN, SiOCH or SiOCN, or SiBCN. The ends of the nanowire stacks remain exposed.
    In FIG. 7, the ends of the nanowires have been encapsulated in an encapsulating material 34, according to a deposition process known per se. Access is provided to the upper face of the sacrificial grids 31 and to the upper face of the sacrificial spacers 32 and 33. FIG. 8 is a view in longitudinal section at one of the stacks of nanowires. At this stage, the nanowires 11 to 17 are stored in their entirety, under the passivation material 34, under the sacrificial spacers 32 and 33, and under the sacrificial grid 31. Due to the continuity of these nanowires between their ends, on the entire stack retains the voltage stresses induced in the silicon nanowires 12, 14, 16 and 18.
    In FIG. 9, a step of removing the sacrificial spacers 32 and 33 is carried out. This removal is here carried out by selective etching of the sacrificial spacers 32 and 33. For sacrificial spacers 32 and 33 formed in SiN, the removal can for example be produced by wet etching with orthophosphoric acid (H3PO4). Grooves 321 and 331 are thus formed on either side of each of the sacrificial grids 31. As better illustrated in FIG. 10, an intermediate middle part of the stacks of nanowires is thus exposed, on either side of the sacrificial grids 31.
    In Figure 11, the exposed parts of the nanowires plumb with the grooves 321 and 331 are here the subject of an ion implantation, other methods of chemical consumption being detailed below. One can for example carry out an ion implantation of silicon, in order to make the exposed SiGe amorphous, or at least to make it rich in defects. The ion implantation here aims to make amorphous or modify the crystal lattice of the SiGe nanowires 11,13,15 and 17, plumb with the grooves 321 and 331. Each nanowire 11 to 17 is then dissociated between:
    a first end housed under the passivation material 34. This first end is not impacted (or so marginally) by the ion implantation step;
    an intermediate part exposed in the groove 321. This intermediate part corresponds to the reference 112 for the SiGe nanowire 11. This intermediate part corresponds to the reference 162 for the silicon nanowire 16;
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    an intermediate part of the channel housed under the sacrificial grid 31. This intermediate part is not impacted (or then marginally) by the ion implantation step. This intermediate part corresponds to the reference 113 for the SiGe 11 nanowire. This intermediate part corresponds to the reference 163 for the silicon nanowire 16;
    an intermediate part exposed in the groove 331. This intermediate part corresponds to the reference 114 for the SiGe nanowire 11. This intermediate part corresponds to the reference 164 for the silicon nanowire 16;
    a second end housed under the passivation material 34. This second end is not impacted (or only marginally) by the ion implantation step. This second end corresponds to the reference 115 for the SiGe 11 nanowire. This second end corresponds to the reference 165 for the silicon nanowire 16.
    The areas of SiGe having been the subject of an ion implantation then become particularly sensitive to a subsequent etching, which will be selective. The ion implantation here takes advantage of the different amorphization thresholds for silicon and germanium. The ion implantation thus makes it possible to carry out an amorphization of the intermediate parts of the SiGe nanowires, without leading to an amorphization of the intermediate parts of the silicon nanowires.
    In order to achieve an ion implantation of the intermediate parts of the SiGe nanowires at different levels of the stack, the ion implantation can be carried out in several stages, with different ionization energies. The ionization energies will for example be designed to present a peak of defects at the level of a respective intermediate portion targeted in a SiGe nanowire. We can for example consider carrying out an ion implantation from Si, P, Ar and Ge.
    In FIG. 12, the intermediate portions of the SiGe nanowires 11, 13, 15 and 17 are removed. This removal is carried out by selective etching of the SiGe made amorphous at the base of the grooves 321 and 331. The ends and the middle part of the SiGe nanowires 11, 13, 15 and 17 remained masked by the passivation material 34 and the sacrificial grid 31 not having been altered by ion implantation, the etching of the SiGe of the intermediate parts being very selective. The intermediate parts removed from the SiGe nanowires 11, 13, 15 and 17 give way to recesses. The nanowire 11 thus has recesses 116 and 117 on either side of its middle part 113. The nanowire 16 thus has recesses above and below its intermediate parts 162 and 164.
    Advantageously, the intermediate parts of the silicon nanowires 12 and 16 can be doped after the intermediate parts of the SiGe nanowires 11, 13, 15 and 17 have been removed. Appropriate doping of the
    ICG11092 EN Depot Texte.docx intermediate parts of Silicon nanowires improves the electrical performance of the transistors to be formed. Such doping can for example be carried out by plasma immersion or by a deposit rich in ions which can diffuse in the intermediate parts of the silicon nanowires.
    In FIG. 13, the recesses previously formed are at least partially filled with a dielectric material, so as to form internal spacers. Thus, the recesses 116 and 117 of the nanowire 11 are here replaced by internal spacers 118 and 119. Advantageously, it is also possible to fill the recesses formed only partially, so as to conserve an air spacer. Such partial filling may for example be carried out by ALD (for atomic layer deposition, Atomic Layer Deposition in English). Such air spacers reduce the dielectric constant of the spacers. Such partial filling still makes it possible to maintain a material between the air and the middle part under the grid to avoid filling this cavity during subsequent steps. Each intermediate part of a silicon nanowire 12, 14 or 16 is thus disposed between two internal spacers in a direction normal to the substrate 100. The internal spacers are made of dielectric, for example a dielectric with a low dielectric constant (typically less than 4 ). The internal spacers are for example made of SiBCN, or of SiOCN or of SiOCH. The internal spacers are typically formed from a material whose etching is very selective compared to the other materials used for the formation of the transistor (for example polysilicon and TiN for the gate, S1O2 for a passivation / encapsulation material, etc.). ).
    In FIGS. 14 and 15, the intermediate parts of the nanowires and the dielectric spacers are coated in spacers 42 and 43, formed on either side of the sacrificial grid 31. The spacers 42 and 43 are advantageously made of dielectric with a low constant dielectric. The spacers 42 and 43 are for example made of SiBCN or SiOCH. From then on, an insulation was created between the sacrificial grid 31 and the ends of the nanowire stacks. As a variant, it is also possible to form the spacers 42 and 43 with the same material and during the same process phase as the internal spacers.
    In Figures 16 and 17, the passivation material 34 was removed, in order to expose the ends of the nanowires 11 to 17. The internal spacers, the spacers 42 and 43 and the sacrificial grid 31 are preserved.
    In FIGS. 18 and 19, a step of removing the ends of the SiGe nanowires 11, 13, 15 and 17 was carried out. This removal of the ends is carried out selectively with respect to the ends of the silicon nanowires 12, 14 and 16. and relative to the spacers and to the sacrificial grid 31. The ends of the silicon nanowires 12, 14 and 16 are then relaxed.
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    At this stage, the intermediate parts of the SiGe nanowires 11, 13, 15 and 17 remain relaxed, the intermediate parts of the silicon nanowires 12, 14 and 16 remain stressed in tension. The ends of the silicon nanowires 12, 14 and 16 are relaxed by removing the ends of the SiGe nanowires 11, 13, 15 and 17.
    In FIGS. 20 and 21, a deposit 10 of SiC: P is formed by epitaxy on either side of the spacers 42 and 43. This deposit is formed around the ends of the nanowires 12, 14 and 16. The deposit 10 thus fills the recesses obtained during the selective removal of the ends of the SiGe nanowires
    11, 13, 15 and 17. The presence of the ends of the nanowires 12, 14 and 16 promotes the growth of the deposit 10 by epitaxy in several directions.
    This deposition of SiC doped in situ with phosphorus makes it possible, on the one hand, to include N-type dopants in the source and the drain of the nMOS transistor to be formed. On the other hand, due to its lattice parameter, the growth by epitaxy of SiC from the ends of the nanowires 12, 14 and 16 which remained exposed will induce a longitudinal tension stress in these nanowires 12, 14 and 16. The stress longitudinal in tension in the middle zone of nanowires 12, 14 and 16 (corresponding to the channel zone of the nMOS transistor to be formed) is then increased. A longitudinal compression stress appears in the middle zone of the SiGe nanowires 11, 13, 15 and 17.
    In FIGS. 22 and 23, the ends of the nanowires 12, 14 and 16 and the deposit of 10 were encapsulated in a passivation material 34.
    In FIGS. 24 and 25, the sacrificial grid 31 is removed, in order to provide a groove 312 and thus access to the middle parts of the nanowires 11 to 17. The removal of the sacrificial grid 31 is for example carried out by selective etching by relative to the material of spacers 42 and 43.
    We then proceeded to a selective etching of the middle part of the nanowires 11, 13, 15 and 17, keeping the middle part of the nanowires 12, 14 and 16. The middle part of the nanowires 12, 14 and 16 (corresponds to the zones of channel of the covering grid transistor being formed) retains its longitudinal voltage stress. Due to the formation of recesses replacing the middle parts of the nanowires 11, 13, 15 and 17, an access to all the faces of the middle parts of the nanowires 12, 14 and 16 is thus formed. The internal spacers 118 and 119, and the spacers 42 and 43 make it possible to protect the intermediate parts of the nanowires 12, 14 and 16 during this selective etching of the SiGe from the middle parts of the nanowires 11, 13, 15 and 17.
    In Figure 26, we proceed to the formation of a gate insulator 44 around the middle parts of the nanowires 12, 14 and 16. The gate insulator of each nanowire
    12, 14 and 16 may for example comprise an interfacial oxide layer in contact with the nanowire, surmounted by a dielectric layer coating this
    ICGl 1092 FR Depot Texte.docx interfacial layer. The dielectric layer can for example be made of HfO 2 .
    In FIGS. 27 and 28, an enveloping grid 41 is formed by filling the recesses surrounding the median parts of the nanowires 12, 14 and 16 and the grid insulators 44. The enveloping grid 41 can for example be made so known per se by depositing a gate metal or by depositing highly doped polysilicon or TiN.
    In the examples described, the intermediate parts of the SiGe nanowires were removed by ion implantation followed by etching. One can also consider removing the intermediate parts of sacrificial nanowires by etching along the crystalline planes of these nanowires. For example, chemical etching can be carried out having a fast etching speed along sparse crystal planes, and a low etching speed along denser crystal planes. It is possible, for example, to etch SiGe along crystalline planes with hydrochloric acid.
    The example described includes a superposition of layers of silicon and silicon germanium in order to create channel zones stressed longitudinally in tension. However, it is also possible to envisage other types of semiconductor materials in this superposition, as soon as one of the materials is suitable for the formation of the channel of a transistor, that its superposition with the other material induces voltage prestresses. in the channel zone for an nMOS (or in compression for a pMOS), and that the two materials can be etched selectively with respect to each other. One can for example consider making a superposition of nanowires of III-V type materials, for example InAs and InGaAs. The nanowire overlap can include nanowires made of at least three different semiconductor materials.
    According to another variant, a voltage stress can be obtained in the channel region of nMOS transistors, from nanowires whose intermediate zone is initially unconstrained.
    At the stage illustrated in FIG. 1, there is then an upper layer 100 of a substrate of the solid semiconductor type (Bulk in English) or SOI (for Silicon on insulator). The semiconductor layer 101 formed on the layer 100 is here a SiGe layer comprising a biaxial compression stress.
    In the step illustrated in FIG. 2, in this variant, a superposition of layers 102 to 107 was formed on the layer of SiGe 101.
    We thus formed an alternation of layers of SiGe 101, 103, 105 and 107, and of silicon layers 102, 104 and 106. Layers 102 to 107 are typically
    ICG11092 FR Depot Texte.docx formed by sequential epitaxy deposit steps. In a manner known per se, due to the differences in lattice parameters between the silicon layers 102, 104 and 106, and the SiGe layers 101, 103, 105 and 107, the Si layers 102, 104 and 106 are relaxed.
    The thickness of the layers 101, 103, 105 and 107 is for example between 5 and 15 nm, preferably at most 10 nm. This thickness is for example 7 nm. The thickness of the layers 102, 104 and 106 is for example between 5 and 15 nm, preferably at most 10 nm. This thickness is for example 9 nm.
    In the step illustrated in FIG. 3, a mask 2 has been formed in this variant on the superposition of layers 101 to 107, for example by photolithography. In FIG. 4, the layers 101 to 107 were etched, so as to form superpositions or stacks of adjacent nanowires. Each superposition or stack of nanowires comprises a superposition of nanowires 11 to 17. The nanowires 11 to 17 extend in a longitudinal direction, and thus have a length at least twice greater than their width or their height. Nanowires 11, 13, 15 and 17 are here in SiGe, for example
    If (ix) Ge x with 0.2 <x <0.6. We can for example take the value x = 0.3. The nanowires 12, 14 and 16 are here made of silicon. Mask 2 has been removed from the stacks. The width of each stack is for example between 10 and 50 nanometers. The nanowire stacks here comprise 7 superimposed nanowires. A different number of superimposed nanowires can of course be used. The height of the nanowire stacks is for example between 30 and 100 nanometers. At this stage, the SiGe nanowires 11, 13, 15 and 17 are constrained in compression and the silicon nanowires 12, 14 and 16 are relaxed.
    In FIG. 5, a sacrificial grid 31 has been formed for each of the nanowire stacks, as for the variant described above.
    In FIG. 6, sacrificial spacers 32 and 33 have been formed, on either side of each of the sacrificial grids 31, as for the variant described above.
    In FIG. 7, the ends of the nanowires have been encapsulated in an encapsulation material 34, as for the variant described above. At the stage illustrated in FIG. 8, the nanowires 11 to 17 are stored in their entirety, under the passivation material 34, under the sacrificial spacers 32 and 33, and under the sacrificial grid 31, as in the variant described above. Due to the continuity of these nanowires between their ends, over the entire stack, retains the compression stresses induced in the SiGe nanowires 11, 13, 15 and 17 and retains relaxation in the silicon nanowires 12, 14 and 16.
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    In FIG. 9, a step of removing the sacrificial spacers 32 and 33 is carried out, as for the variant described above. As best illustrated in FIG. 10, an intermediate middle part of the nanowire stacks is thus exposed, on either side of the sacrificial grids 31.
    In FIG. 11, the exposed parts of the nanowires plumb with the grooves 321 and 331 are here the subject of an ionic implantation of silicon, in order to make the exposed SiGe amorphous, or at least to make it rich in defects , as for the variant described above. Each nanowire 11 to 17 is then dissociated between
    a first end housed under the passivation material 34 not impacted by the ion implantation step;
    an intermediate part exposed in the groove 321, corresponding to the reference 112 for the SiGe 11 nanowire, corresponding to the reference 162 for the silicon nanowire 16;
    an intermediate channel part housed under the sacrificial grid 31, not impacted by the ion implantation step, corresponding to the reference 113 for the SiGe nanowire 11, corresponding to the reference 163 for the silicon nanowire 16;
    an intermediate part exposed in the groove 331 corresponding to the reference 114 for the SiGe nanowire 11, corresponding to the reference 164 for the silicon nanowire 16;
    a second end housed under the passivation material 34 not impacted by the ion implantation step, corresponding to the reference 115 for the SiGe nanowires 11, corresponding to the reference 165 for the silicon nanowire 16.
    The areas of SiGe having been the subject of an ion implantation then become particularly sensitive to a subsequent etching, which will be selective, as detailed above. Ion implantation can be performed with the detailed parameters for the variant described above.
    In FIG. 12, the intermediate parts of the SiGe nanowires 11, 13, 15 and 17 are removed, as in the variant described above. The intermediate parts removed from the SiGe nanowires 11,13,15 and 17 give way to recesses. The nanowire 11 thus has recesses 116 and 117 on either side of its middle part 113. The nanowire 16 thus has recesses above and below its intermediate parts 162 and 164.
    The intermediate parts of the silicon nanowires 12, 14 and 16 can be doped after the intermediate parts of the nanowires have been removed.
    SiGe 11, 13, 15 and 17, as proposed for the variant described above.
    In FIG. 13, the recesses previously formed are at least partially filled with a dielectric material, to form the internal spacers 118
    ICGl 1092 FR Depot Texte.docx et 119, as for the variant described above. Each intermediate part of a silicon nanowire 12, 14 or 16 is thus placed between two internal spacers in a direction normal to the substrate 100.
    In FIGS. 14 and 15, the intermediate parts of the nanowires and the dielectric spacers are coated in spacers 42 and 43, formed on either side of the sacrificial grid 31, as in the variant described above.
    In Figures 16 and 17, the passivation material 34 was removed, in order to expose the ends of the nanowires 11 to 17, the internal spacers, the spacers 42 and 43 and the sacrificial grid 31 being preserved as in the variant described previously.
    In FIGS. 18 and 19, a step of removing the ends of the SiGe nanowires 11, 13, 15 and 17 was carried out, as in the variant described above. The ends of the silicon nanowires 12, 14 and 16 are then relaxed.
    At this stage, the intermediate parts of the SiGe nanowires 11, 13, 15 and 17 remain relaxed, the intermediate parts of the silicon nanowires 12, 14 and 16 remain stressed in tension. The ends of the silicon nanowires 12, 14 and 16 are relaxed by removing the ends of the SiGe nanowires 11, 13, 15 and 17.
    In FIGS. 20 and 21, a deposit 10 of SiC: P is formed by epitaxy on either side of the spacers 42 and 43, as in the variant detailed above, the deposit 10 thus filling the recesses obtained during the selective removal of the ends of the SiGe nanowires 11, 13, 15 and 17.
    This deposition of SiC doped in situ with phosphorus makes it possible, on the one hand, to include N-type dopants in the source and the drain of the nMOS transistor to be formed. On the other hand, due to its lattice parameter, the growth by epitaxy of SiC from the ends of the nanowires 12, 14 and 16 which remained exposed will induce a longitudinal tension stress in these nanowires 12, 14 and 16. A stress longitudinal in tension in the middle zone of nanowires 12, 14 and 16 (corresponding to the channel zone of the nMOS transistor to be formed) appears. The longitudinal compression stress decreases in the middle zone of the SiGe nanowires 11, 13, 15 and 17.
    In FIGS. 22 and 23, the ends of the nanowires 12, 14 and 16 and the deposit of 10 were encapsulated in a passivation material 34.
    In FIGS. 24 and 25, the sacrificial grid 31 is removed, in order to provide a groove 312 and thus access to the middle parts of the nanowires 11 to 17. The removal of the sacrificial grid 31 is for example carried out by selective etching by relative to the material of spacers 42 and 43.
    We then proceeded to a selective etching of the middle part of the nanowires 11, 13, 15 and 17, keeping the middle part of the nanowires 12, 14 and
    ICG11092 EN Text Depot.docx
    16, as in the variant described above, the middle part of the nanowires 12, 14 and 16 retaining its longitudinal stress in tension.
    In FIG. 26, a grid insulator 44 is formed around the middle parts of the nanowires 12, 14 and 16, as in the variant described above.
    In FIGS. 27 and 28, a coating grid 41 is formed by filling the recesses surrounding the middle parts of the nanowires 12, 14 and 16 and the grid insulators 44, as in the variant described above.
    The invention has essentially been described previously in its application to an nMOS transistor. Alternatively, one can obtain a compressive stress in the channel region of pMOS transistors.
    At the stage illustrated in FIG. 1, there is then an upper layer 100 of a substrate of the solid semiconductor type (Bulk in English) or SOI (for Silicon on insulator). The semiconductor layer 101 formed on the layer 100 is here a SiGe layer comprising a biaxial compression stress.
    In the step illustrated in FIG. 2, in this variant, a superposition of layers 102 to 107 was formed on the layer of SiGe 101, as for the variants described above.
    In the step illustrated in FIG. 3, a mask 2 has been formed in this variant on the superposition of layers 101 to 107, for example by photolithography. In FIG. 4, the layers 101 to 107 have been etched, so as to form superpositions or stacks of adjacent nanowires, as for the variants described above. At this stage, the SiGe nanowires 11, 13, 15 and 17 are constrained in compression and the silicon nanowires 12, 14 and 16 are relaxed.
    In FIG. 5, a sacrificial grid 31 has been formed for each of the nanowire stacks, as for the variant described above. In FIG. 6, sacrificial spacers 32 and 33 have been formed, on either side of each of the sacrificial grids 31, as for the variant described above.
    In FIG. 7, the ends of the nanowires have been encapsulated in an encapsulation material 34, as for the variant described above. At the stage illustrated in FIG. 8, the nanowires 11 to 17 are stored in their entirety, under the passivation material 34, under the sacrificial spacers 32 and 33, and under the sacrificial grid 31, as in the variant described above. Due to the continuity of these nanowires between their
    ICGl 1092 FR Depot Texte.docx ends, over the entire stack, retains the compression stresses induced in SiGe nanowires 11, 13, 15 and 17 and retains relaxation in Silicon nanowires 12, 14 and 16.
    In FIG. 9, a step of removing the sacrificial spacers 32 and 33 is carried out, as for the variants described above. As best illustrated in FIG. 10, an intermediate middle part of the nanowire stacks is thus exposed, on either side of the sacrificial grids 31.
    In FIG. 11, the exposed parts of the nanowires plumb with the grooves 321 and 331 are here the subject of an ionic implantation of silicon, in order to make the exposed SiGe amorphous, or at least to make it rich in defects , as for the variants described above. Each nanowire 11 to 17 is then dissociated between:
    a first end housed under the passivation material 34 not impacted by the ion implantation step;
    an intermediate part exposed in the groove 321, corresponding to the reference 112 for the SiGe 11 nanowire, corresponding to the reference 162 for the silicon nanowire 16;
    an intermediate channel part housed under the sacrificial grid 31, not impacted by the ion implantation step, corresponding to the reference 113 for the SiGe nanowire 11, corresponding to the reference 163 for the silicon nanowire 16;
    an intermediate part exposed in the groove 331 corresponding to the reference 114 for the SiGe nanowire 11, corresponding to the reference 164 for the silicon nanowire 16;
    a second end housed under the passivation material 34 not impacted by the ion implantation step, corresponding to the reference 115 for the SiGe nanowires 11, corresponding to the reference 165 for the silicon nanowire 16.
    The areas of SiGe having been the subject of an ion implantation then become particularly sensitive to a subsequent etching, which will be selective, as detailed above. Ion implantation can be performed with the detailed parameters for the variants described above.
    In FIG. 12, the intermediate parts of the SiGe nanowires 11, 13, 15 and 17 are removed, as in the variant described above. The intermediate parts removed from the SiGe nanowires 11,13,15 and 17 give way to recesses. The nanowire 11 thus has recesses 116 and 117 on either side of its middle part 113. The nanowire 16 thus has recesses above and below its intermediate parts 162 and 164.
    ICGl 1092 FR Text Depot.docx
    The intermediate parts of the silicon nanowires 12, 14 and 16 can be doped after the withdrawal of the intermediate parts of the SiGe nanowires 11, 13, 15 and 17, as proposed for the variants described above.
    In FIG. 13, the recesses formed previously are at least partially filled with a dielectric material, to form the internal spacers 118 and 119, as for the variant described above. Each intermediate part of a silicon nanowire 12, 14 or 16 is thus placed between two internal spacers in a direction normal to the substrate 100.
    In FIGS. 14 and 15, the intermediate parts of the nanowires and the dielectric spacers are coated in spacers 42 and 43, formed on either side of the sacrificial grid 31, as in the variants described above.
    In Figures 16 and 17, the passivation material 34 was removed, in order to expose the ends of the nanowires 11 to 17, the internal spacers, the spacers 42 and 43 and the sacrificial grid 31 being preserved as in the variants described previously.
    In FIGS. 18 and 19, a step of removing the ends of the SiGe nanowires 11, 13, 15 and 17 was carried out, as in the variants described above. The ends of the silicon nanowires 12, 14 and 16 are then relaxed.
    At this stage, the intermediate parts of the SiGe nanowires 11, 13, 15 and 17 remain relaxed, the intermediate parts of the silicon nanowires 12, 14 and 16 remain stressed in tension. The ends of the silicon nanowires 12, 14 and 16 are relaxed by removing the ends of the SiGe nanowires 11, 13, 15 and 17.
    In FIGS. 20 and 21, a deposit 10 of SiGe is formed by epitaxy on either side of the spacers 42 and 43. This deposit is formed around the ends of the nanowires 12, 14 and 16. The deposit 10 thus fills the recesses obtained during the selective removal of the ends of the SiGe nanowires 11, 13, 15 and
    17. The presence of the ends of the nanowires 12, 14 and 16 promotes the growth of the deposit 10 by epitaxy in several directions.
    This deposition of SiGe in situ by epitaxy from the ends of the nanowires 12, 14 and 16 which remained exposed makes it possible, because of its lattice parameter, to induce a longitudinal compressive stress in these deposits. This induces a longitudinal compressive stress in the middle region of the nanowires 12, 14 and 16 (corresponding to the channel region of the pMOS transistor to be formed) appears. The longitudinal compression stress increases in the middle zone of the SiGe nanowires 11, 13, 15 and 17.
    In FIGS. 22 and 23, the ends of the nanowires 12, 14 and 16 and the deposit of 10 were encapsulated in a passivation material 34.
    ICG11092 EN Text Depot.docx
    In FIGS. 24 and 25, the sacrificial grid 31 is removed, in order to provide a groove 312 and thus access to the middle parts of the nanowires 11 to 17. The removal of the sacrificial grid 31 is for example carried out by selective etching by relative to the material of spacers 42 and 43.
    We then proceeded to a selective etching of the middle part of the nanowires 11, 13, 15 and 17, keeping the middle part of the nanowires 12, 14 and 16. The middle part of the nanowires 12, 14 and 16 has its longitudinal constraint in compression increase.
    In FIG. 26, a grid insulator 44 is formed around the middle parts of the nanowires 12, 14 and 16, as in the variants described above.
    In FIGS. 27 and 28, a covering grid 41 is formed by filling the recesses surrounding the middle parts of the nanowires 12, 14 and 16 and the grid insulators 44, as in the variants described above.
    In the examples described above, the nanowires have a substantially square cross section. Other cross sections can of course be envisaged, for example ovoid, trapezoidal or rectangular. Nanowires in the form of nanowires can for example be used, and thus have a cross section in which the width is at least equal to 2 times the height.
    In the examples described above, the overlay includes seven nanowires. It is also possible to provide a superposition of any number of suitable nanowires, at least equal to 2.
    ICG11092 EN Text Depot.docx
    权利要求:
    Claims (15)
    [1" id="c-fr-0001]
    1. Method for manufacturing a field effect transistor with a covering gate (41), characterized in that it comprises the steps of:
    -providing a substrate surmounted by a superposition of first to third nanowires (11-17) each having a middle part and first and second ends on either side of the middle part along a longitudinal axis, each of these nanowires formed of semiconductor material, said second nanowire being disposed between the first and third nanowires and being formed of a semiconductor material different from that of the first nanowire and different from that of the third nanowire, so that the first or second nanowire is subjected to mechanical stress along its longitudinal axis, the middle part of the first to third nanowires being covered by a sacrificial grid (31), of electrical insulation coating an intermediate part of the second nanowire between its middle part and its first end and between its middle part and its second end, said electrical insulator separating the first extremi tee of the middle part of the first and third nanowires, and separating the second end of the middle part of the first and third nanowires;
    - removal of the first and second ends of the first and third nanowires (11,13);
    -deposition of a semiconductor material (10) different from that of the first to third nanowires, by growth by epitaxy from the first and second ends of the second nanowire, so as to modify the mechanical stress in the middle part of the second nanowire ; then
    -removing said sacrificial grid (31) and removing the middle part of the first and third nanowires (11, 13);
    -forming a gate electrode (44) coating the middle part of said second nanowire (12).
    [2" id="c-fr-0002]
    2. Method for manufacturing a field effect transistor with a covering gate (41) according to claim 1, in which said first to third nanowires supplied include silicon, the first and third nanowires including a proportion of germanium greater than that of second nanowire.
    [3" id="c-fr-0003]
    3. Method for manufacturing a field effect transistor with a covering gate (41) according to claim 2, in which the first and third nanowires supplied are in
    If (ix) Ge x with 0.2 <x <0.6.
    ICG11092 EN Text Depot.docx
    [4" id="c-fr-0004]
    4. A method of manufacturing a field effect transistor with a covering gate (41) according to claim 2 or 3, wherein said deposited semiconductor material is SiC doped in situ with Phosphorus.
    [5" id="c-fr-0005]
    5. A method of manufacturing a field effect transistor with a covering gate (41) according to claim 2 or 3, wherein said deposited semiconductor material is SiGe doped in situ with Boron.
    [6" id="c-fr-0006]
    6. A method of manufacturing a field effect transistor with a covering gate (41) according to claim 5, in which said deposited semiconductor material has a higher concentration of Germanium than that of the first and third nanowires.
    [7" id="c-fr-0007]
    7. A method of manufacturing a field effect transistor with a covering gate (41) according to any one of the preceding claims, in which said second nanowire of the supplied substrate is relaxed.
    [8" id="c-fr-0008]
    8. A method of manufacturing a field effect transistor with a covering gate (41) according to any one of claims 1 to 6, wherein said second nanowire of the supplied substrate is voltage-constrained along its longitudinal axis.
    [9" id="c-fr-0009]
    9. Method for manufacturing a field effect transistor with a covering gate (41) according to any one of the preceding claims, comprising preliminary steps of:
    removal of intermediate portions of first and third initially continuous nanowires (11, 13), between their first end and their middle part on the one hand, and between their second end and their middle part on the other hand; -deposit of said insulator.
    [10" id="c-fr-0010]
    10. A method of manufacturing a field effect transistor with a covering gate (41) according to claim 9, wherein said step of removing the intermediate parts of the first and third nanowires comprises an ion implantation in these intermediate parts then a step of selective engraving of these parts.
    [11" id="c-fr-0011]
    11. A method of manufacturing a field effect transistor with a covering gate (41) according to claim 9, wherein said step of removing the intermediate parts of the first and third nanowires (11,13) comprises an etching of said intermediate parts of the first and third nanowires according to their crystalline planes.
    ICG11092 EN Text Depot.docx
    [12" id="c-fr-0012]
    12. A method of manufacturing a field effect transistor with a covering gate (41) according to any one of the preceding claims, further comprising a step of doping the second nanowire (12) in an intermediate part between its first end and its middle part and in a part
    5 intermediate between its second end and its middle part, after the step of supplying the substrate and before the step of removing the sacrificial grid (31).
    [13" id="c-fr-0013]
    13. Method for manufacturing a field effect transistor with a covering gate (41)
    10 according to any one of the preceding claims, in which said first to third nanowires supplied have a thickness at most equal to 15 nm.
    [14" id="c-fr-0014]
    14. Method for manufacturing a field effect transistor with a covering gate (41)
    [15" id="c-fr-0015]
    15 according to any one of the preceding claims, in which said electrical insulator for the substrate supplied has a thickness of between 3 and 15 nm between the first end and the middle part of the first and third nanowires.
    ICG11092 EN Text Depot.docx
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    引用文献:
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    WO2013095651A1|2011-12-23|2013-06-27|Intel Corporation|Non-planar gate all-around device and method of fabrication thereof|
    WO2013095650A1|2011-12-23|2013-06-27|Intel Corporation|Nanowire structures having non-discrete source and drain regions|
    US20160027870A1|2014-07-25|2016-01-28|International Business Machines Corporation|Fabrication of perfectly symmetric gate-all-around fet on suspended nanowire using interface interaction|
    US9397179B1|2015-02-17|2016-07-19|Samsung Electronics Co., Ltd.|Semiconductor device|
    EP3070744A1|2015-03-16|2016-09-21|Commissariat à l'Energie Atomique et aux Energies Alternatives|Improved method for producing a transistor in a stack of vertically adjacent semiconductor layers|
    US9647139B2|2015-09-04|2017-05-09|International Business Machines Corporation|Atomic layer deposition sealing integration for nanosheet complementary metal oxide semiconductor with replacement spacer|WO2018182655A1|2017-03-30|2018-10-04|Intel Corporation|Removal of a bottom-most nanowire from a nanowire device stack|
    US10297663B2|2017-04-19|2019-05-21|International Business Machines Corporation|Gate fill utilizing replacement spacer|
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    优先权:
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    FR1659942|2016-10-13|FR1659942A| FR3057703B1|2016-10-13|2016-10-13|METHOD FOR MANUFACTURING A COILGROUND FIELD EFFECT TRANSISTOR|
    US15/782,105| US10147788B2|2016-10-13|2017-10-12|Process for fabricating a field effect transistor having a coating gate|
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